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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
TOSHIBA is not responsible for any incorrect or incomplete information. Information is subject to change at any time without notice.
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Arm® Cortex®-M3 has two privileged levels (Privilege/Non-privilege) and two operation modes (Thread/Handler).
For embedded usage, a basic configuration with only privileged level or a configuration to switch between Privilege and Non-privilege can be selected.
At the privileged/non-privileged level, by switching between the main stack (MSP) and process stack (PSP) assigned to register R13, the stack area can be separated and managed by processing functions such as the OS kernel and user routines.
* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.