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Operation Mode and Stack Pointer (1)

Arm® Cortex®-M3 has two privileged levels (Privilege/Non-privilege) and two operation modes (Thread/Handler).
For embedded usage, a basic configuration with only privileged level or a configuration to switch between Privilege and Non-privilege can be selected.
At the privileged/non-privileged level, by switching between the main stack (MSP) and process stack (PSP) assigned to register R13, the stack area can be separated and managed by processing functions such as the OS kernel and user routines.

Basic system
System using RTOS

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
NVIC (Nested Vectored Interrupt Controller)
Main Core
Register Configuration
The Role of the Register
PC, LR
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
The Role of NVIC
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (1)
Vector Table (2)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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