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Basic Configuration of CMOS Logic ICs

Example of the cross section of a CMOS logic IC

  • A wide diffusion region (p-well) is formed in the n-substrate.
  • An n-channel MOSFET is formed on the p-well.
  • A p-channel MOSFET is formed on the n-substrate.
  • An n-well is formed on a p-substrate, depending on the process.
  • Since the performance and integration density of MOSFETs are determined by the gate width, the manufacturing process is expressed with the gate width. For example, a CMOS process with a gate width of 1.0 μm is called a 1.0-μm CMOS process.
    (In this case, the gate width is the distance between #3 and #4 and between #5 and #6.)
Basic configuration of CMOS Logic ICs

#1. N-substrate: Typically, a wafer substrate
#2. P-well: Region for forming an n-channel MOSEFT
#3. Diffused region for the source of the n-channel MOSFET
#4. Diffused region for the drain of the n-channel MOSFET
#5. Diffused region for the drain of the p-channel MOSFET
#6. Diffused region for the source of the p-channel MOSFET
#7. Diffused region for p-well bias
#8. Diffused region for n-substrate bias

Chapter2 Basic Operations of CMOS Logic ICs

What is a CMOS Logic IC?
Basic CMOS Logic ICs
Basic Operations of CMOS Logic ICs

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