Vector Table (1)

Vector Table (1)

The start address of the handler (processing routine) for each exception type is set respectively.
When an exception or interrupt event occurs, the exception handler fetch starts at its address.
The vector table of each exception type is shown below

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
NVIC (Nested Vectored Interrupt Controller)
Main Core
Register Configuration
The Role of the Register
PC, LR
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (1)
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
The Role of NVIC
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (2)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

A new window will open