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What can I do to increase the switching speed of a bias resistor built-in transistor (BRT)?

The switching speed of the bipolar transistor is defined as shown in Figure 1.
It takes the rise time (tr) for the BRT to turn on whereas it takes the sum of the storage time (tstg) and the fall time (tf) for the BRT to turn off. Table 1 shows examples of the results of measurements of these BRT characteristics.
The measurements were taken at a VCC of 5 V, switching the input voltage from 0 V to 5 V and vice versa. The load resistance is 1 kΩ.

Type R1 R2 tr (ns) tstg (μs) tf (μs)
RN1401 4.7 4.7 38 1.89 0.11
RN1402 10 10 60 2.25 0.13
RN1403 22 22 118 2.41 0.21
Figure 1 Test circuit for and definitions of switching times
Figure 1 Test circuit for and definitions of switching times

Table 1 Examples of the results of measurements of BRT switching times

BRTs are mainly used as switches and remain in the saturation region while they are on. Therefore, the storage time (tstg), i.e., the time required to remove minority carriers from the base, accounts for the dominant portion of the switching time.
There are two considerations for reducing tstg:

a) Removing excessive carriers quickly
Excessive carriers accumulated in the base are removed mainly through R2 although the carrier removal path slightly differs, depending on the configuration of the preceding circuit. (If the output of the preceding circuit has low impedance at Low level, excessive carriers are also removed through R1). Therefore, BRTs with a low R2 value are suitable for increasing the switching speed.

b) Minimize the accumulation of excessive carriers.
This means that the depth of saturation of the BRT is reduced while it is on. To minimize the accumulation of excessive carriers, it is necessary to reduce the current applied to the base of the internal transistor (Ib). This can be achieved by 1) reducing the input current to the BRT (IB) and 2) reducing the base current of the internal transistor (i.e., increasing the current flowing to R2). Therefore, BRTs with a large R1 value and a large resistor ratio (R1/R2) are suitable. Note, however, that minimizing the accumulation of excessive carriers might reduce the depth of saturation, causing VCE(sat) to increase.

Table 2 When the R2 value is changed
Table 2 When the R2 value is changed
Table 2 When the R1 value is changed
Table 2 When the R1 value is changed
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