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Sequential Logic: Latches

Latches
Example: 74VHC373

A latch can retain data under specific conditions.
There are several types of latches such as D-type and RS (Reset and Set) latches. As an example, the following describes the operation of a D-type latch.
For example, a D-type latch has an input data pin (D), a latch enable pin (LE), and an output data pin (Q). In this case, when LE is Low, Q retains the previous value of D. When LE is High, Q follows the changes of D. The following shows the timing diagram of a D-type latch.

Logic symbol and truth table  of a D-type latch
Logic symbol and truth table of a D-type latch
Logic schematic of a D-type latch
Logic schematic of a D-type latch
Timing diagram of a D-type latch
Timing diagram of a D-type latch

Chapter3 Basic CMOS Logic ICs

Basic CMOS Logic ICs
Combinational Logic: Inverters and Buffers
Combinational Logic: Bidirectional Bus Buffers
Combinational Logic: Schmitt-Trigger Devices
Combinational Logic: Decoders
Combinational Logic: Multiplexers
Combinational Logic: Analog Multiplexer/Demultiplexers
Combinational Logic: Analog Switches
Sequential Logic: Flip-Flops
Sequential Logic: Counters
Sequential Logic: Shift Registers

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