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Do bidirectional bus buffers have any constraints on the timing of the direction (DIR), bus, and other signals?

The following shows an equivalent circuit for a bidirectional bus buffer and its truth table.

Equivalent circuit for a bidirectional bus buffer





A Bus

B Bus











High Impedance ( Z )

X:Don’t care

Although this bus buffer allows the signal direction to be switched easily, the following considerations apply:

1.  Ensure that the outputs of the bus buffer do not enter into conflict with the outputs of other buffers when DIR changes state.
→ A conflict causes not only an abnormal output condition but also excessive current, possibly damaging these devices.
2.  Ensure that the inputs do not float (i.e., are not left open or in the High-Z state).
→ A floating input is easily affected by electromagnetic susceptibility (EMS) and might cause an abnormal output condition or output oscillation as parasitic capacitances are charged by leakage current.

Therefore, when the /G pin is used, it is necessary to pull all I/O pins up to VCC or down to GND. When the /G pin is fixed Low, it is necessary to pull unused I/O pins up to VCC or down to GND.
The following describes the timing requirements using the circuit and timing diagrams shown below.
A bidirectional bus buffer is connected between the A bus and the B bus. In the initial state, the A pin is an input, and the B pin is an output. Therefore, a signal is transmitted from the A bus to the B bus. At this time, Buffer Y is disabled (i.e., provides no output).

Bidirectional bus buffer

1.  Disable the bidirectional bus buffer by setting the /G pin High. It takes a period of tpLZ for the bus buffer to be disabled. Then, the A and B pins assume the Hi-Z state. It is therefore necessary to stabilize their potential by connecting, for example, pull-up resistors (Rpullup1 and Rpullup2) to these pins. Bus buffers with a bushold capability do not require any pull-up resistors.
2.  The output enters into a conflict after the signal direction changes. Therefore, disable the output of Buffer X and enable the output of Buffer Y while the bus buffer is disabled. Also, set the direction pin (DIR) from Low to High during this period.
3.  Enable the bus buffer by setting the /G pin Low.

The internal circuit changes its mode while the DIR pin changes state (from Low to High or High to Low) and while the enable pin (/G or /OE) changes state. During these periods, the output value is indeterminate, meaning it cannot be determined whether the output is High, Low, or between High and Low. Take this into consideration when creating a design since the output value during these periods cannot be guaranteed.

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