For >3-pin packages (TO-247)
The back electromotive voltage VLS (=LS*dID/dt) is generated by the inductance component L Source of the source wire and the slope dI dID/dt of the drain current of the voltage VGS applied between the gate and the source of the FET chip. The actual applied voltage is reduced from the set gate voltage by this back electromotive force, and the switching speed, especially turn-on, is slowed down.
For >4-pin packages (TO-247-4L)
Moving the source terminal on the drive side from a location close to the FET chip separated from the source wire on the load side makes it less susceptible to the drive voltage. This makes it possible to improve the high-speed switching performance of the FET chip.
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