General-Purpose Logic ICs
Common
- What are the differences among the general-purpose logic ICs?
- What are the differences between "Absolute Maximum Ratings" and "Operating Ranges" of the general purpose logic ICs?
- What is the tolerant function of the general-purpose logic ICs?
- In what sequence should I turn on and off the power and input signals of a general purpose logic IC?
- Is a decoupling capacitor required for the supply of a general purpose logic IC?
- Is it possible to leave the unused inputs of the general purpose logic ICs open?
- What is bushold of the general-purpose logic ICs?
- How should unused output pins of the general-purpose logic ICs be handled?
- Is there a specification for the input-signal rise time and fall time of the general-purpose logic ICs?
- Are there any regulations for the capacitance of the capacitor attached to the output terminal of a general-purpose logic IC?
- Is it possible to short-circuit the outputs of multiple general-purpose logic ICs?
- Is it possible to configure a wired OR circuit by connecting output terminals in general-purpose logic ICs?
- How can I find the maximum operating frequency of a general-purpose logic IC?
- How many amperes is the output current of a general-purpose logic IC able to drive?
- What is fanout of a general-purpose logic IC?
- How can the power dissipation of a general-purpose logic IC be calculated?
- What kind of faults could occur if static electricity is discharged (ESD) into a general-purpose logic IC?
CMOS Logic ICs
- Is the output status of the sequential circuit such as flip-flops, registers, counters, and one-shot multivibrators determined after the power is turned on?
- Are there any problems with the input pins of CMOS logic ICs and the bus pins (input/output pins) of bidirectional bus buffers in a floating state?
- What countermeasures should be taken for signals with a low slew rate (signals with slow input rise and fall times)is input?
- What is the main reason why a CMOS logic IC is unstable?
- What are the possible causes when the output voltage of CMOS logic ICs does not rise to the power supply voltage?
- When a CMOS logic IC is switched, what is the measure for the voltage-waveform (overshoot or undershoot) like the spike that occurs at the output terminal?
- What are the possible causes of noise in the voltage waveform input to the CMOS logic IC
- What is the difference between CMOS logic IC 04 (inverter) and U04 (unbuffered inverter)?
Bus Switches
- What is a bus switch?
- How should unused terminals of bus switches and analog switches be handled?
- What is the difference between a bus switch and an analog switch?
- What do SPST and SPDT in bus switches mean?
- What is the difference between CMOS logic IC multiplexers and bus switch multiplexers?
- Does the bus switch have a tolerant function?
- How should I select a bus switch?
- Is there a bus switch that can switch high-speed signals (USB3.0/3.1, PCIe™3.0, etc.)?
- Are there any restrictions on the power up/down order of the dual power supply bus switch?
- Can the power of the bus switch is turn off while the signal on?
- What are the leaks in a dual power bus switch?
- What is Break Before Make (TBBM)?
Level Shifters
- What types of voltage level translation ICs (level shifters) are available?
- In order to achieve a step-down (5 V → 3.3 V) and step-up (3.3 V → 5 V) level shift (voltage conversion), how should this be achieved?
- How can I achieve level shifting from 2.5 V to 1.8 V and vice versa?
- Are there level shifters (voltage translation IC) compatible with serial communication standards (UART, I2C)?
- What is the difference between the bus switch type and the buffer type of the voltage-level transformation IC (level shifter)?
- In what order should the voltage level translation IC (level shifter) of the dual power supply type be powered up and the signals input?
- Do bidirectional bus buffers have any constraints on the timing of the direction (DIR), bus, and other signals?
- Is it necessary to pull up the input/output pins of dual power supply bus switch?
- How can I calculate the maximum operating frequency of a level shifter (voltage translation logic IC)?
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