Understanding MOSFET Operation Principles and Mechanisms | Cutoff, Linear, and Saturation Regions Explained

A MOSFET has three terminals: drain, source, and gate, and its on/off state is controlled by the voltage between the gate and source.
There are three operating regions: the cutoff region (off state), and two on states—the linear region and the saturation region.
When the gate-to-source voltage exceeds the threshold voltage (V_th), an inversion layer forms beneath the gate, turning the MOSFET on. If the drain-to-source voltage is lower than the pinch-off voltage (VP), the MOSFET operates in the linear region; if higher, part of the inversion layer becomes a depletion region, and the MOSFET operates in the saturation region. In saturation, the drain current remains almost constant regardless of V_DS.
To understand this in more detail, knowledge of the MOS capacitor is necessary.
MOSFETs have lateral and vertical structures, but here we focus on the lateral structure. For differences between lateral and vertical types, see FAQ:　MOSFET structure.

Important: V_th in this section refers to the MOSFET gate threshold voltage. Do not confuse this with the thermal voltage used in BJT calculations—they are completely different concepts.

In a MOSFET, a channel layer (inversion layer) is formed between the drain and source due to the potential difference between the gate and source, and the MOSFET turns on. The on and off states are explained using Figure 4.

1. No bias state: V_GS = 0: A depletion layer is formed between the buried n-type region and the p-type substrate. 
2. Depletion state: V_GS < V_th: When a positive voltage is applied to the gate, the electrode side becomes positively charged and the semiconductor side becomes negatively charged, which offsets the holes in the P-type semiconductor and creates a depletion layer directly below the gate.
   These two states are the off state of a MOSFET.
3. Inversion state: V_GS ≧ V_th: If the gate voltage increases further, electrons gather directly below the gate electrode and an inversion layer is formed.
   This creates a state similar to that of an n-type semiconductor, and the source and gate are connected by this inversion layer. In the case of an N-ch MOSFET, the inversion layer is in a state where there is an excess of free electrons, so it has the same properties as an n-type semiconductor. The drain and source are connected by this inversion layer This inversion layer forms a channel between the drain and source through which current can flow.
   This inversion state is called the on-state of the MOSFET. The on-state of a MOSFET can be in two states: the linear region and the saturation region, as shown in Figure 1. Each state is determined by the voltage V_DS applied between the drain and source.
4. On in the linear region 0 < V_DS ≦ V_GS – V_th : The inversion layer becomes shallower closer to the drain, but it is formed continuously between the drain and source. Therefore, I_D flows in a manner nearly proportional to V_DS.
5. On in the saturation region V_DS ≧ V_GS – V_th : The inversion layer is discontinued near the drain. The drain current (electrons injected from the source) flows through the depletion layer between the inversion layer and the drain. However, the drain current is almost constant when V_GS is fixed.

To gain a deeper understanding, it is important to understand MOS capacitors.
The MOS capacitor is the area enclosed by the dotted line in Figure 3. Figure 5 shows the MOS capacitor and energy band states for states 1 to 3 described in Figure 4. The MOS capacitor is rotated 90° to the left to match the energy band diagram.
The MOS capacitor of an N-channel MOSFET consists of a metal electrode and a p-type substrate sandwiched between an insulating film. This MOS capacitor's state changes depending on the voltage between the electrode (G), which corresponds to the gate of the MOSFET, and the back gate (B). Since the back gate and source are short-circuited and have the same potential, we use the V_GS parameter commonly used for MOSFETs.

1. No bias state:
   The energy state is as shown in the figure. In this state, nothing is generated directly below the insulating film. In this example, the work function Φ_m of the metal and the work function Φ_S of the p-type semiconductor (the difference between the Fermi level and the vacuum level) are considered identical, resulting in no band bending (flat band state). However, they are usually different, which causes band bending. The difference in work functions (Φ_S - Φ_m) is called the flat band voltage.
2. Depletion state:
   A voltage of 0<V_GS<V_th is applied, causing band bending. The applied voltage causes the impurities (such as B) that make up the p-type to capture electrons, forming a depletion layer only on the p-type semiconductor side. (The reason the gate side drops even though a positive voltage is applied to the gate side is because the energy band diagram is based on electrons.) 
3. Inversion state:
   When V_th<V_GS is applied, the band bends further. Near the insulating film, this bending causes the Fermi level E_F to become higher than the intrinsic Fermi level E_i, resulting in inversion from p-type to n-type. Electrons, which are p-type minority carriers, accumulate in this area.

In this way, the state of the MOS capacitance changes depending on the voltage V_GS applied between the electrode (G) and backgate (B). The MOSFET is turned on and off by switching between the inversion state and other states.
However, another state occurs due to the voltage applied between the drain and source, which is not considered here. This is saturation. 

MOSFET has two on-states: the linear region and the saturation region (see Fig. 1). When the gate voltage V_GS exceeds the threshold voltage V_th and the MOSFET turns on, as the drain voltage V_DS increases, the inversion layer (channel) near the drain becomes depleted and the inversion layer is cut off. The voltage at this boundary is called the pinch-off voltage V_P, expressed as V_P = V_GS - V_th. The condition for saturation is V_DS ≥ V_GS - V_th.
When entering the saturation state, even if V_DS is increased, the drain current I_D becomes almost constant. The reason why it becomes constant is explained below.
When V_GS > V_th and V_DS = 0V, the potential difference between the gate and the p-type semiconductor is the same near the source and near the drain, and a uniform inversion layer is formed (see Fig. 6).

When V_GS > V_th and a voltage V_DS is applied between the drain and source, the source side is 0V and the drain side is V_DS. When V_DS is applied, the potential in the inversion layer changes continuously from the source to the drain (see Fig. 7).

If the distance from the source to the drain is L, the potential at position x is V_(x), and the potential difference between the gate and the substrate at that position is expressed as:
V_GS(x)=V_GS–V_(x)
If this potential difference is greater than V_th, the inversion layer is formed; if less, only a depletion region exists.

• If V_GS – V_(x) ≥ V_th, an inversion layer is formed.
• If V_GS − V_(x) < V_th (for positions from x to L), only a depletion region exists.

The case where V_GS − V_(x’) = V_th occurs is shown in Fig. 8.

The position where V_GS − V_(x’) = V_th is called the pinch-off point. From the pinch-off point to the drain end, the region becomes a depletion layer. Although the depletion layer contains almost no carriers, as shown in the energy band diagram in Fig. 9, there is no diffusion barrier from source to drain. Therefore, electrons are accelerated by the electric field through the depletion layer and reach the drain.

Therefore, the drain current is determined by the voltage applied to the inversion layer up to this x’ (V_GS − V_th) and the channel resistance of that section. If this resistance is R_ch(sat), the drain current in saturation is expressed as:
I_D(sat) = (V_GS − V_th) / R_ch(sat)
For this reason, in the saturation state, the drain current hardly depends on V_DS. However, as V_DS increases, the pinch-off point moves toward the source, the channel length becomes shorter, R_ch(sat) decreases, and I_D slightly increases (channel length modulation effect). Fig. 10 shows the increase state in actual products.

[Supplement]

Short-channel products and channel length modulation effect
The increase in drain current due to channel length modulation effect is more pronounced in short-channel MOSFETs. This is because the relative change in effective channel length due to pinch-off is larger in short-channel devices. Short-channel products are devices designed with extremely short channel lengths, such as MOSFETs used in advanced logic ICs and high-speed switching applications with the latest advanced process technology. The shorter the channel length, the larger the λ (channel length modulation coefficient), and the greater the slope of current increase in the saturation region.

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