The MOSFETs in a CMOS logic IC make switching transitions while charging and discharging internal and external load capacitances. The trace impedance during switching can be regarded as an LCR circuit. Since the switching current (i) flows through inductance (L), a spike voltage (=L(di/dt)) appears on the VCC and GND lines of the CMOS logic IC. This noise is called switching noise.
Multiple simultaneously switching outputs draw a large charge/discharge current and therefore cause a large switching noise (called simultaneous switching noise). The following lists the measures for the reduction of switching noise.
Countermeasures to reduce switching noise:
(1) Increase the width and reduce the length of VCC and GND lines to reduce their inductance.
(2) Place a bypass capacitor between and as close as possible to the VCC and GND pins of the CMOS logic IC (See below figure).
(3) Exercise care as to clock and reset signals. Unused inputs of gates such as drivers should be connected to either VCC or GND. Connect a low-pass filter to the output of used gates to remove noise.
(4) Select low-noise ICs.
(5) Add a damping resistor to the output of used gates (See below figure). It is necessary to adjust the value of the damping resistor by checking the output waveform.
* Toshiba provides CMOS ICs with an internal damping resistor (See below figure), which help reduce not only switching noise but also parts count.