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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
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The depletion layer spreads differently in N-layer, which determines the limit of the breakdown voltage. SJ-MOS can be designed with N-layers with lower resistivity, allowing for lower on-resistance.
SJ-MOS (we call it DTMOS) forms a columnar P layer (P-pillar layer) on a part of N-layer and alternates P-N layers.
When VDS is applied, the depletion layer spreads over N-layer, which is the drifting layer. However, the spreads differently in the common D-MOS (called π-MOS in our case) and SJ-MOS. (See the electric field intensity diagram. The electric field intensity indicates the state in the depletion layer.)
In D-MOS, the interface between P/N-layers has the highest electric field strength, and breakover (breakdown phenomena) occurs when this part exceeds the limit of the material-silicon. This is the limit of the breakdown voltage. On the other hand, SJ-MOS has uniform electric field strength in N-layers.
As a consequence, SJ-MOS can be designed with lower-resistance N-layers, allowing for lower on-resistance.
Please also refer to FAQ below.