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Main Core
The Cortex®-M3 main core has a three-stage pipeline configuration.
- [Fe] Fetch stage
Reads the instruction of the memory address indicated by the PC (Program Counter)
- [De] Decode stage
Decodes the instruction and determines the execution control of the execution stage
- [Ex] Execution stage
Executes four arithmetic operations by the Shift and ALU (Arithmetic Logic Unit), logical operations, operations such as multiplication and division, and Load and Store
The update of the register is performed at this stage. - [MUL/DIV] Multiplication/Division
Chapter 2 Arm® Cortex®-M3
* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.