2-13. Tail Chain Control by NVIC

Timing improvement of exception/interrupt operation processing
Arm® Cortex®-M3 has become high-speed PUSH/POP processing through control of the NVIC.
In addition, if the interrupt request occurs at the same time or a high-priority interrupt request occurs during interrupt processing, the automatic save of registers by PUSH/POP is omitted, and the processing timing is improved.

Tail Chain Control by NVIC
Tail Chain Control by NVIC
Tail Chain Control by NVIC

第2章 Arm® Cortex®-M3

2-1. Hardware Configuration
Details
2-2. NVIC (Nested Vectored Interrupt Controller)
Details
2-3. Main Core
Details
2-4. Register Configuration
Details
2-5. The Role of the Register
Details
2-6. PC, LR
Details
2-7. Stack Pointer
Details
2-8. PUSH/POP to the Stack Pointer
Details
2-9. Special Register
Details
2-10-1. Operation Mode and Stack Pointer (1)
Details
2-10-2. Operation Mode and Stack Pointer (2)
Details
2-11. Exceptions (Reset, Interrupt, Fault, System Call)
Details
2-12. The Role of NVIC
Details
2-14. Memory Map
Details
2-15. Memory Map for Arm® Cortex®-M3 Specifications
Details
2-16. Memory Map of TMPM330: Example of TX03 Series
Details
2-17-1. Vector Table (1)
Details
2-17-2. Vector Table (2)
Details
2-18-1. Bit Band Area and Bit Band Alias Area (1)
Details
2-18-2. Bit Band Area and Bit Band Alias Area (2)
Details

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