2-4. Register Configuration

Register Configuration

Cortex®-M3 processors have registers R0 to R15.
R0 to R12 are general-purpose registers.
R13 is a register with a bank configuration that switches between two types of stack pointers.
R14 is the link register and R15 is the program counter.
Special registers that control the special features of the Cortex®-M3 processor are also available.

Chapter 2 Arm® Cortex®-M3

2-1. Hardware Configuration
2-2. NVIC (Nested Vectored Interrupt Controller)
2-3. Main Core
2-5. The Role of the Register
2-6. PC, LR
2-7. Stack Pointer
2-8. PUSH/POP to the Stack Pointer
2-9. Special Register
2-10-1. Operation Mode and Stack Pointer (1)
2-10-2. Operation Mode and Stack Pointer (2)
2-11. Exceptions (Reset, Interrupt, Fault, System Call)
2-12. The Role of NVIC
2-13. Tail Chain Control by NVIC
2-14. Memory Map
2-15. Memory Map for Arm® Cortex®-M3 Specifications
2-16. Memory Map of TMPM330: Example of TX03 Series
2-17-1. Vector Table (1)
2-17-2. Vector Table (2)
2-18-1. Bit Band Area and Bit Band Alias Area (1)
2-18-2. Bit Band Area and Bit Band Alias Area (2)

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