(1) SJ-MOS has pillar-shaped P layer (P pillar layer) in N layer. P and N layers are aligned alternately. (See Fig. 3-9(b).)
(2) Depletion layer spreads in N- layer by applying VDS, but the way it spreads in SJ-MOS is different from the case of general D-MOS. (See Fig. 3-9(a)/(b) for electric field intensity. Electric field intensity indicates the status of depletion layer.)
(3) In the case of D-MOS the electric field intensity is the strongest at P/N- layer interface. When the electric field intensity exceeds the limit of silicon, break-over phenomenon (breakdown phenomenon) occurs, and this is the voltage limit. On the other hand, in the case of SJ-MOS, the electric field intensity is uniform in N layer.
(4) As a result, SJ-MOS can be designed with N layer that has lower resistance, realizing low-ON-resistance products.
SJ-MOS can realize lower ON resistance with the same size chip as DMOS.