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About information presented in this cross reference

The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
TOSHIBA is not responsible for any incorrect or incomplete information. Information is subject to change at any time without notice.

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Find everything you need for your next product design. Simply select an application and click through to the block diagram to discover our semiconductor solutions.

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Vector Table (2)

Vector Table (2)

As an example, a list of interrupt factors for TMPM330 is shown.

Vector Table (2)

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
NVIC (Nested Vectored Interrupt Controller)
Main Core
Register Configuration
The Role of the Register
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (1)
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
The Role of NVIC
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (1)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.