Hardware Configuration

The Arm® Cortex®-M3 processor functional block schematic for the TX03 series is shown below.
It consists of a main core block, an NVIC (Nested Vectored Interrupt Controller) block that controls interrupts, a functional block for debug support, and an interface block for an external connection with peripheral circuits.

Hardware Configuration

[Fe] Fetch stage
[De] Decode stage
[Ex] Execution stage
[MUL/DIV] Multiplication/Division

Hardware Configuration

Chapter 2 Arm® Cortex®-M3

NVIC (Nested Vectored Interrupt Controller)
詳細資料
Main Core
詳細資料
Register Configuration
詳細資料
The Role of the Register
詳細資料

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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