Hardware Configuration

The Arm® Cortex®-M3 processor functional block schematic for the TX03 series is shown below.
It consists of a main core block, an NVIC (Nested Vectored Interrupt Controller) block that controls interrupts, a functional block for debug support, and an interface block for an external connection with peripheral circuits.

Hardware Configuration

[Fe] Fetch stage
[De] Decode stage
[Ex] Execution stage
[MUL/DIV] Multiplication/Division

Hardware Configuration

Chapter 2 Arm® Cortex®-M3

NVIC (Nested Vectored Interrupt Controller)
Main Core
Register Configuration
The Role of the Register
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (1)
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
The Role of NVIC
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (1)
Vector Table (2)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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