Countermeasures for ESD Protection

CMOS logic ICs provide electrostatic discharge (ESD) immunity compliant with international standards. Exposure to higher ESD might cause a malfunction or permanent damage to a CMOS logic IC.
Because the oxide film at the input gate of a CMOS logic IC is very thin (hundreds to thousands of angstroms), it could be damaged by an ESD of hundreds to thousands of volts.

To prevent this, each input pin generally provides ESD protection circuitry. However, there is a limit to this protection. Insert external ESD protection diodes for the inputs that might be exposed to excessive ESD (e.g., inputs connected to a board’s external interface).

There are various ESD models. The following describes one of the major ESD models.

Human body model (HBM)
This model characterizes the susceptibility of a semiconductor device to damage from ESD that might be generated from a human body.
There are numerous discussions on the human body capacitance. For ESD immunity testing, the charged human body is modeled by a 100-pF capacitor and a 1500-Ω　discharging resistor. During testing, the capacitor is fully charged and then discharged through a resistor.

The HBM test circuit is shown below.